FIG. 2 shows a cross-sectional view of a prior art two-phase charge transfer device (hereinafter referred to as a CCD) in the charge transfer direction. In FIG. 2, reference numeral 5 designates a p-type substrate. An n.sup.- -type layer 3 in which buried channels are formed is disposed on the substrate 5. P-type impurity channels 4 are disposed in the n.sup.- -type layer 3 to determine the transfer direction of a two-phase CCD. Respective first polycrystalline silicon electrodes 1 are disposed between corresponding channels opposite n.sup.- -type layer 3. Second polycrystalline silicon electrodes 2 are disposed opposite the channels 4 and partly opposite the first polycrystalline silicon electrodes 1. An intervening film 6, e.g., a thermal oxide film, is disposed on the first polycrystalline silicon electrodes 1 and is produced when a second layer gate oxide film is produced. Generally, the first and second electrodes are alternatingly driven as gates .phi.1 and .phi.2, enabling transfer of signal charges in the direction shown in FIG. 2.
Recently, integrated solid-state imaging device technology has been advancing, and a CCD having more than 10,000 stages is needed. The method of driving such a CCD has been a problem.
As is apparent from FIG. 2, the driving gates .phi.1 and .phi.2 present a capacitive load and include inter-phase and anti-ground capacitances. FIG. 3 shows an equivalent circuit including the capacitances .phi.1 and .phi.2 which result in problems in driving the CCD. In FIG. 3, reference character C.sub.ov designates an overlapping capacitance between the first and the second polycrystalline silicon electrodes 1 and 2. Reference character C.sub.ox designates a gate oxide film capacitance of the respective gate. Reference character CJ designates the capacitance of a transfer channel. From this equivalent circuit, the gate electrode capacitance C is represented by: ##EQU1## where N is the number of CCD stages. This gate electrode capacitance is obtained when the driving gate .phi.1 or .phi.2 is at ground voltage.
The advancement of a highly integrated solidstate imaging device requires a high transfer speed. However, in a CCD including more than 10,000 stages, the driving circuit of the CCD is overloaded and it is difficult to transfer charges at high speed. In the CCD of the above-described construction, charge transfer is usually effected with a rectangular pulse. However, when the load is too large, the rectangular pulse is too weak. When the pulse power is increased, power dissipation is inevitably increased.
In order to solve these problems, a CCD is driven by a resonant circuit including an inductance and a capacitance, exploiting the capacitive load of the CCD.
FIG. 4(a) shows a CCD driving circuit utilizing a resonant circuit which was reported by Ito et al at page 79 of the 1987 National Meeting of the Society of Television Engineers. This driving circuit is quite effective for reducing power dissipation. In FIG. 4(a), reference numeral 7 designates a clock driver. Reference numeral 8 designates an equivalent capacitance C(.phi.1-.phi.2). Reference numeral 9 designates a dumping resistance R. Reference numeral 10 designates an inductance L. Reference numeral 11 designates a capacitance C.sub.s. Reference numerals 12 and 13 designate clock inputs having inverted phases.
When the rectangular waves f.sub.1 and f.sub.2 shown in FIG. 4(b) are input to the clock drivers 7, the load viewed from the clock driver 7 is a resonant circuit having parallel and serial resonance frequencies f.sub.1 and f.sub.2 as shown in the following equations. ##EQU2## Therefore, when the circuit characteristics are optimized, sinusoidal waves shown by .phi.1 and .phi.2 of FIG. 4(c) are applied to the driving gate of the CCD. The charging and discharging energy of the equivalent capacitance C(.phi.1-.phi.2) is stored in the resonant circuit, and the power supplied from the external terminals f.sub.1 and f.sub.2 is reduced. However, there is a problem in that the equivalent capacitance of the CCD is not constant or it varies in accordance with the clock voltage applied to the gate and the amount of charge that is transferred; that is, as the capacitance of the transfer channel C.sub.j in FIG. 3 varies, the equivalent capacitance C(.phi.1-.phi.2) also varies. As a result, the resonant frequency inevitably varies.